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Enabling in-memory computation of binary BLAS using ReRAM crossbar arrays., , and . VLSI-SoC, page 1-6. IEEE, (2016)FPGA-based Deep Learning Inference Accelerators: Where Are We Standing?, , , , , and . ACM Trans. Reconfigurable Technol. Syst., 16 (4): 60:1-60:32 (December 2023)Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design., , , , , and . CoRR, (2016)Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization., , , , , , and . CoRR, (2018)Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization., , , , , and . IEEE Trans. Parallel Distributed Syst., 29 (8): 1707-1720 (2018)Nano Security: From Nano-Electronics to Secure Systems., , , , , , , , , and 13 other author(s). DATE, page 1334-1339. IEEE, (2021)Hardware Security Primitives Using Passive RRAM Crossbar Array: Novel TRNG and PUF Designs., , , , , and . ASP-DAC, page 449-454. ACM, (2023)Finite State Automata Design using 1T1R ReRAM Crossbar., , , , , , , , and . NEWCAS, page 1-5. IEEE, (2023)A Parallel SystemC Virtual Platform for Neuromorphic Architectures., , and . ISQED, page 1-6. IEEE, (2022)A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications., , , , , , , and . LATS, page 1-4. IEEE, (2022)