( en | de | ru )

 

Disambiguation of "Bhawmik, Sudipta"

Author of the publication

copydeleteadd this publication to your clipboard
An almost full-scan BIST solution-higher fault coverage and shorter test application time.

, , and . ITC, page 1065-1073. IEEE Computer Society, (1998)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Sudipta Majumdar

Sudipta Das

Sudipta Sengupta

Sudipta Kundu

Sudipta Basu

 

Other publications of authors with the same name

An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch., , , and . J. Electron. Test., 18 (4-5): 475-485 (2002)Core Based ASIC Design., and . VLSI Design, page 10. IEEE Computer Society, (2000)Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme., , and . DAC, page 748-753. ACM Press, (1999)Selecting test methodologies for PLAs and random logic modules in VLSI circuits - an expert systems approach., , and . Integr., 7 (3): 267-281 (1989)KIDLAN: A hardware description language., , , and . Microprocessing and Microprogramming, 26 (1): 1-13 (1989)DFT Expert: designing testable VLSI circuits., and . IEEE Des. Test, 6 (5): 8-19 (1989)The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data., , , , , and . ITC, page 998-1007. IEEE Computer Society, (2003)Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch., , , , and . ASP-DAC/VLSI Design, page 598-603. IEEE Computer Society, (2002)A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis., , and . DAC, page 554-559. ACM Press, (1998)POWERTEST: A Tool for Energy Conscious Weighted Random Pattern Testing., , and . VLSI Design, page 416-422. IEEE Computer Society, (1999)