( en | de | ru )

 

Disambiguation of "Jang, Young-Chan"

Author of the publication

copydeleteadd this publication to your clipboard
A 10-Gb/s Dual-Loop Reference-less CDR with FD Controller.

, , , , , and . ISOCC, page 109-110. IEEE, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Young Jang Kim

Chan-Young Park

Grady Leon Young

Christopher Young

Charlotte Young

 

Other publications of authors with the same name

A 1 V 200 kS/s 10-bit Successive Approximation ADC for a Sensor Interface., , and . IEICE Trans. Electron., 94-C (11): 1798-1801 (2011)A 2-Gb/s CMOS SLVS Transmitter with Asymmetric Impedance Calibration for Mobile Interfaces., and . IEICE Trans. Electron., 97-C (8): 837-840 (2014)A 3.0 Gsymbol/s/lane MIPI C-PHY Receiver with Adaptive Level-Dependent Equalizer for Mobile CMOS Image Sensor., , and . Sensors, 21 (15): 5197 (2021)An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock., , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (4): 1386-1396 (2017)An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme., , , , , , , , , and 9 other author(s). ISSCC, page 527-536. IEEE, (2006)Performance analysis of structural similarity-based backlight dimming algorithm modulated by controlling allowable local distortion of output image., , , and . Displays, (2019)A 10-bit 20-MS/s Asynchronous SAR ADC with Meta-Stability Detector Using Replica Comparators., , , , , , , and . IEICE Trans. Electron., 99-C (6): 651-654 (2016)An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator., , , , and . IEICE Trans. Electron., 90-C (6): 1156-1164 (2007)An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 42 (1): 193-200 (2007)BER Measurement of a 5.8-Gb/s/pin Unidirectional Differential I/O for DRAM Application With DIMM Channel., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 44 (11): 2987-2998 (2009)