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Disambiguation of "Soeken, Mathias"

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Exact Synthesis of Boolean Functions in Majority-of-Five Forms.

, , , , , and . ISCAS, page 1-5. IEEE, (2019)

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Mathias Soeken

Bernd Soeken

Gerhard Soeken

Heinrich Soeken

Mathias Rafler

Gaussian loop- and Pólya processes: a point process approach. Uni Potsdam, (2009)
 

Other publications of authors with the same name

Three-Input Gates for Logic Synthesis., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (10): 2184-2188 (2021)Design and Automation for Quantum Computation and Quantum Technologies., , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 12 (3): 581-583 (2022)Mapping NCV Circuits to Optimized Clifford+T Circuits., , and . RC, volume 8507 of Lecture Notes in Computer Science, page 163-175. Springer, (2014)On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis., , , , and . DATE, page 1649-1654. IEEE, (2019)A Resource Estimation and Verification Workflow in Q# Special session paper., , , , and . DATE, page 1050-1055. IEEE, (2021)Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications., , , and . DAC, page 74. ACM, (2019)Integrated ESOP Refactoring for Industrial Designs., , , , , and . ICECS, page 369-372. IEEE, (2018)Compiling Permutations for Superconducting QPUs., , , and . DATE, page 1349-1354. IEEE, (2019)Improvements to boolean resynthesis., , , , , , , and . DATE, page 755-760. IEEE, (2018)A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks., , , , and . DATE, page 568-573. IEEE, (2020)