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Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators.

S. Khan, A. Khalid, C. Rafferty, Y. Shah, M. O'Neill, W. Lee, and S. Hwang. VLSI-SoC, page 1-6. IEEE, (2023)

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Ciara Moore

Ciara Kelbling

Franco Ciaraldi-Schoolmann

Other publications of authors with the same name

Accelerating Homomorphic Encryption using Approximate Computing Techniques.S. Khanna, and C. Rafferty. ICETE (2), page 380-387. ScitePress, (2020)Compact and provably secure lattice-based signatures in hardware.J. Howe, C. Rafferty, A. Khalid, and M. O'Neill. ISCAS, page 1-4. IEEE, (2017)Addressing Side-Channel Vulnerabilities in the Discrete Ziggurat Sampler.S. Brannigan, M. O'Neill, A. Khalid, and C. Rafferty. SPACE, volume 11348 of Lecture Notes in Computer Science, page 65-84. Springer, (2018)Optimized Schoolbook Polynomial Multiplication for Compact Lattice-Based Cryptography on FPGA.W. Liu, S. Fan, A. Khalid, C. Rafferty, and M. O'Neill. IEEE Trans. Very Large Scale Integr. Syst., 27 (10): 2459-2463 (2019)On Practical Discrete Gaussian Samplers for Lattice-Based Cryptography.J. Howe, A. Khalid, C. Rafferty, F. Regazzoni, and M. O'Neill. IEEE Trans. Computers, 67 (3): 322-334 (2018)Error Samplers for Lattice-Based Cryptography -Challenges, Vulnerabilities and Solutions.A. Khalid, C. Rafferty, J. Howe, S. Brannigan, W. Liu, and M. O'Neill. APCCAS, page 411-414. IEEE, (2018)Time-independent discrete Gaussian sampling for post-quantum cryptography.A. Khalid, J. Howe, C. Rafferty, and M. O'Neill. FPT, page 241-244. IEEE, (2016)High Performance Modular Multiplication for SIDH.W. Liu, Z. Ni, J. Ni, C. Rafferty, and M. O'Neill. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 3118-3122 (2020)Acceleration of Post Quantum Digital Signature Scheme CRYSTALS-Dilithium on Reconfigurable Hardware.D. Campbell, C. Rafferty, A. Khalid, and M. O'Neill. FPL, page 462-463. IEEE, (2022)Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators.S. Khan, A. Khalid, C. Rafferty, Y. Shah, M. O'Neill, W. Lee, and S. Hwang. VLSI-SoC, page 1-6. IEEE, (2023)

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Disambiguation of "Rafferty, Ciara"

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Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators.

Please choose a person to relate this publication to

Ciara Moore

Ciara Kelbling

Franco Ciaraldi-Schoolmann

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Rafferty, Ciara"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators.

Please choose a person to relate this publication to

Ciara Moore

Ciara Kelbling

Franco Ciaraldi-Schoolmann

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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Efficient, Error-Resistant NTT Architectures for CRYSTALS-Kyber FPGA Accelerators.