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A Standardized Interface Control Unit for Heterogeneous Digital Signal Processors.

, and . ISCAS, page 97-100. IEEE, (1994)

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Fault-Tolerant Neural Architectures: The Use of Rotated Operands., , and . ISCAS, page 2201-2204. IEEE, (1995)Merged CORDIC Algorithm., and . ISCAS, page 1988-1991. IEEE, (1995)A fast hybrid carry-lookahead/carry-select adder design., , and . ACM Great Lakes Symposium on VLSI, page 149-152. ACM, (2001)A self-testing method for the pipelined A/D converter., , and . ISCAS (1), page 109-112. IEEE, (2003)A variable-precision interval arithmetic processor., and . ASAP, page 248-258. IEEE, (1994)FFT Implementation with Fused Floating-Point Operations., and . IEEE Trans. Computers, 61 (2): 284-288 (2012)Design of High-Speed Wide-Word Hybrid Parallel-Prefix/Carry-Select and Skip Adders., , , , and . J. Signal Process. Syst., 90 (3): 409-419 (2018)32 bit single cycle nonlinear VLSI cell for the ICA algorithm., and . ICASSP, page 1429-1432. IEEE, (2008)ASIC evaluation of ECHO hash function., , and . SoCC, page 387-390. IEEE, (2009)JavaFlow - A Java dataflow machine., and . SoCC, page 211-214. IEEE, (2009)