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FUSE: Fusing STT-MRAM into GPUs to Alleviate Off-Chip Memory Access Overheads., , and . HPCA, page 426-439. IEEE, (2019)Using data replication to reduce communication energy on chip multiprocessors., , , and . ASP-DAC, page 769-772. ACM Press, (2005)Optimizing embedded applications using programmer-inserted hints., and . ASP-DAC, page 157-160. ACM Press, (2005)Leveraging value locality for efficient design of a hybrid cache in multicore processors., , , and . ICCAD, page 1-8. IEEE, (2017)Multiverse: Dynamic VM Provisioning for Virtualized High Performance Computing Clusters., , , , , and . CCGRID, page 131-141. IEEE, (2020)Performance aware secure code partitioning., , and . DATE, page 1122-1127. EDA Consortium, San Jose, CA, USA, (2007)Memory bank aware dynamic loop scheduling., , , and . DATE, page 1671-1676. EDA Consortium, San Jose, CA, USA, (2007)Adaptive prefetching for shared cache based chip multiprocessors., , and . DATE, page 773-778. IEEE, (2009)Optimising power efficiency in trace cache fetch unit., , , and . IET Comput. Digit. Tech., 1 (4): 334-348 (2007)Selective Caching: Avoiding Performance Valleys in Massively Parallel Architectures., , and . PDP, page 290-298. IEEE, (2020)