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A Compiled-Code Parallel Pattern Logic Simulator With Inertial Delay Model., , и . J. Inf. Sci. Eng., 15 (6): 885-897 (1999)Flip-Flop Selection for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits., и . J. Inf. Sci. Eng., 16 (5): 687-702 (2000)A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus., , , и . IEEE Trans. Very Large Scale Integr. Syst., 17 (2): 306-311 (2009)Identifying invalid states for sequential circuit test generation., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (9): 1025-1033 (1997)A programmable multiple-sequence generator for BIST applications., и . Asian Test Symposium, стр. 279-285. IEEE Computer Society, (1995)An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits., и . Asian Test Symposium, стр. 173-178. IEEE Computer Society, (1999)All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses., , , , и . DATE, стр. 527-531. IEEE Computer Society / ACM, (2000)Modeling and testing of interference faults in the nano NAND Flash memory., , и . DATE, стр. 527-531. IEEE, (2012)Multilevel full-chip routing with testability and yield enhancement., , , , и . SLIP, стр. 29-36. ACM, (2005)An On-Chip Jitter Measurement Circuit for the PLL., и . Asian Test Symposium, стр. 332-335. IEEE Computer Society, (2003)