Author of the publication

Area-efficient high speed decoding schemes for turbo/MAP decoders.

, , and . ICASSP, page 2633-2636. IEEE, (2001)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Low complexity, high speed decoder architecture for quasi-cyclic LDPC codes., and . ISCAS (6), page 5786-5789. IEEE, (2005)Memory-reduced MAP decoding for double-binary convolutional Turbo code., , and . ISCAS, page 469-472. IEEE, (2010)An Efficient 4-D 8PSK TCM Decoder Architecture., , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (5): 808-817 (2010)Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (9): 2156-2169 (2019)ALT: Area-Efficient and Low-Latency FPGA Design for Torus Fully Homomorphic Encryption., , , and . IEEE Trans. Very Large Scale Integr. Syst., 32 (4): 645-657 (April 2024)A New ACD-OMP Accelerator With Clustered Computing Look-Ahead., , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (9): 1449-1453 (September 2023)A Universal Approximation Method and Optimized Hardware Architectures for Arithmetic Functions Based on Stochastic Computing., , , , , , and . IEEE Access, (2020)Efficient Homomorphic Convolution Designs on FPGA for Secure Inference., , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (11): 1691-1704 (2022)Unified Architecture for Reed-Solomon Decoder Combined With Burst-Error Correction., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (7): 1346-1350 (2012)An Efficient High-Throughput Structured-Light Depth Engine., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (8): 1047-1058 (2022)