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On the fault coverage of delay fault detecting tests.

, and . EURO-DAC, page 334-338. IEEE Computer Society, (1990)

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Other publications of authors with the same name

On the computation of the ranges of detected delay fault sizes., and . ICCAD, page 126-129. IEEE Computer Society, (1989)On the design of path delay fault testable combinational circuits., and . FTCS, page 374-381. IEEE Computer Society, (1990)On Multiple Path Propagating Tests for Path Delay Faults., and . ITC, page 393-402. IEEE Computer Society, (1991)On Unified Delay Fault Testing., and . VLSI Design, page 265-268. IEEE Computer Society, (1993)Design of Scan-Based Path-Delay-Testable Sequential Circuits., and . ITC, page 962-971. IEEE Computer Society, (1993)Distributed Solutions to the Delay Fault Test Quality Evaluation Problem., and . HPDC, page 177-185. IEEE, (1994)Parallel, multi-DUT testing in an open architecture test system., , and . ITC, page 9. IEEE Computer Society, (2005)Parallel Delay Fault Coverage and Test Quality Evaluation., and . ITC, page 113-122. IEEE Computer Society, (1995)On the Detection of Delay Faults., and . ITC, page 845-856. IEEE Computer Society, (1988)On the fault coverage of delay fault detecting tests., and . EURO-DAC, page 334-338. IEEE Computer Society, (1990)