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C3PU: Cross-Coupling Capacitor Processing Unit Using Analog-Mixed Signal In-Memory Computing for AI Inference.

, , , , and . CoRR, (2021)

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FPGA realization of speech encryption based on modified chaotic logistic map., , , and . ICIT, page 1412-1417. IEEE, (2018)FPGA Implementation of the Fractional Order Integrator/Differentiator: Two Approaches and Applications., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (4): 1484-1495 (2019)High speed special function unit for graphics processing unit., , , and . IDT, page 24-29. IEEE, (2014)FPGA realization of a speech encryption system based on a generalized modified chaotic transition map and bit permutation., , , and . Multim. Tools Appl., 78 (12): 16097-16127 (2019)Security and Efficiency of Feistel Networks Versus Discrete Chaos for Lightweight Speech Encryption., , , , and . ICM, page 92-95. IEEE, (2018)FPGA realization of ALU for mobile GPU., , and . ACTEA, page 16-20. IEEE, (2016)Speech encryption using generalized modified chaotic logistic and tent maps., , , and . ICIT, page 1526-1531. IEEE, (2018)Generic Hardware of Fractional Order Multi-Scrolls Chaotic Generator Based on FPGA., , , , and . NEWCAS, page 1-4. IEEE, (2019)Reduce Computing Complexity of Deep Neural Networks Through Weight Scaling., , , and . ISCAS, page 1249-1253. IEEE, (2022)A switched chaotic encryption scheme using multi-mode generalized modified transition map., , , , and . Multim. Tools Appl., 80 (4): 5373-5402 (2021)