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Free Kronecker decision diagrams and their application to Atmel 6000 series FPGA mapping., и . EURO-DAC, стр. 8-13. IEEE Computer Society, (1994)A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits., , и . IEEE Trans. Computers, 49 (3): 267-276 (2000)A Comprehensive Approach to Logic Synthesis and Physical Design for Two-Dimensional Logic Arrays., , , и . DAC, стр. 321-326. ACM Press, (1994)A Cost Minimization Approach to Synthesis of Linear Reversible Circuits., и . CoRR, (2014)Quantum ternary parallel adder/subtractor with partially-look-ahead carry., и . J. Syst. Archit., 53 (7): 453-464 (2007)Quantum Machine Learning, Logic Minimization, and Circuit Design by Optimizing Ternary-Input Binary-Output Kronecker Reed-Muller Forms., , и . FLAP, 9 (3): 733-780 (2022)Quantum Algorithms for Unate and Binate Covering Problems with Application to Finite State Machine Minimization., и . FLAP, 10 (6): 993-1023 (2023)Term Trees in Application to an Effective and Efficient ATPG for AND-EXOR and AND-OR Circuits., , и . VLSI Design, 14 (1): 107-122 (2002)Multi-Level Logic Synthesis Based on Kronecker Decision Diagrams and Boolean Ternary Decision Diagrams for Incompletely Specified Functions., , , и . VLSI Design, 3 (3-4): 301-313 (1995)Quantum-based algorithm and circuit design for bounded Knapsack optimization problem., и . Quantum Inf. Comput., 20 (9&10): 766-786 (2020)