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Tunable Voltage-Mode Subthreshold CMOS Neuron., , , and . ISVLSI, page 252-257. IEEE, (2020)A Novel TFET 8T-SRAM Cell with Improved Noise Margin and Stability., , , and . DDECS, page 39-44. IEEE, (2018)Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology., , , , , , , and . Microelectron. J., 45 (1): 23-34 (2014)A new asymmetric 6T SRAM cell with a write assist technique in 65 nm CMOS technology., , and . Microelectron. J., 45 (11): 1556-1565 (2014)A Low-Noise High Input Impedance Analog Front-End Design for Neural Recording Implant., , , , , and . ICECS, page 887-890. IEEE, (2019)Comparative study of FinFETs versus 22nm bulk CMOS technologies: SRAM design perspective., , , and . SoCC, page 449-454. IEEE, (2014)A 53GΩ@DC Input Impedance Multi-Channel Neural Recording Amplifier with 0.77 μVrms Input-Referred Noise for Deep Brain Implants., , , , and . CICC, page 1-2. IEEE, (2021)Spin-Torque-Nano-Oscillator based neuromorphic computing assisted by laser., , , , , , and . DTIS, page 1-5. IEEE, (2019)Energy-Efficient Spintronic-Based Neuromorphic Computing System Using Current Mode Track and Termination Circuit., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (9): 2915-2923 (September 2023)STT-RAM Energy Reduction Using Self-Referenced Differential Write Termination Technique., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (2): 476-487 (2017)