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K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM.

J. Saikia, S. Yin, Z. Jiang, M. Seok, and J. sun Seo. ISLPED, page 1-6. IEEE, (2019)

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Himangshu Saikia

Ashima Saikia

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K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM.J. Saikia, S. Yin, Z. Jiang, M. Seok, and J. sun Seo. ISLPED, page 1-6. IEEE, (2019)PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference.S. Yin, B. Zhang, M. Kim, J. Saikia, S. Kwon, S. Myung, H. Kim, S. Kim, M. Seok, and J. sun Seo. VLSI Circuits, page 1-2. IEEE, (2021)A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity.S. Venkataramanaiah, J. Meng, H. Suh, I. Yeo, J. Saikia, S. Cherupally, Y. Zhang, Z. Zhang, and J. Seo. IEEE J. Solid State Circuits, 58 (7): 1885-1897 (2023)A Low-Overhead Dynamic TCAM With Pipelined Read-Restore Refresh Scheme.S. Mishra, T. Mahendra, J. Saikia, and A. Dandapat. IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (5): 1591-1601 (2018)FP-IMC: A 28nm All-Digital Configurable Floating-Point In-Memory Computing Macro.J. Saikia, A. Sridharan, I. Yeo, S. Venkataramanaiah, D. Fan, and J. Seo. ESSCIRC, page 405-408. IEEE, (2023)A 28nm 8-bit Floating-Point Tensor Core based CNN Training Processor with Dynamic Activation/Weight Sparsification.S. Venkataramanaiah, J. Meng, H. Suh, I. Yeo, J. Saikia, S. Cherupally, Y. Zhang, Z. Zhang, and J. sun Seo. ESSCIRC, page 89-92. IEEE, (2022)PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference.B. Zhang, S. Yin, M. Kim, J. Saikia, S. Kwon, S. Myung, H. Kim, S. Kim, J. Seo, and M. Seok. IEEE J. Solid State Circuits, 58 (5): 1436-1449 (May 2023)A Low-Voltage 13T Latch-Type Sense Amplifier with Regenerative Feedback for Ultra Speed Memory Access.V. Tripathi, S. Mishra, J. Saikia, and A. Dandapat. VLSID, page 341-346. IEEE Computer Society, (2017)Modeling and Optimization of SRAM-based In-Memory Computing Hardware Design.J. Saikia, S. Yin, S. Cherupally, B. Zhang, J. Meng, M. Seok, and J. Seo. DATE, page 942-947. IEEE, (2021)A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks.B. Zhang, J. Saikia, J. Meng, D. Wang, S. Kwon, S. Myung, H. Kim, S. Kim, J. sun Seo, and M. Seok. CICC, page 1-2. IEEE, (2022)

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Disambiguation of "Saikia, Jyotishman"

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K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM.

Please choose a person to relate this publication to

Himangshu Saikia

Ashima Saikia

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Disambiguation

BibSonomy

Disambiguation of "Saikia, Jyotishman"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM.

Please choose a person to relate this publication to

Himangshu Saikia

Ashima Saikia

Other publications of authors with the same name

Disambiguation

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URL
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K-Nearest Neighbor Hardware Accelerator Using In-Memory Computing SRAM.