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A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise Reduction., , и . ISSCC, стр. 270-271. IEEE, (2013)Digital post-correction of front-end track-and-hold circuits in ADCs., , , и . ISCAS, IEEE, (2006)A 19 µW 20 MHz All-Digital PLL for 2-tone envelope detection radios., , , и . ISCAS, стр. 321-324. IEEE, (2014)A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS., , , , и . ISSCC, стр. 388-389. IEEE, (2010)26.2 A 5.5fJ/conv-step 6.4MS/S 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme., , , , , и . ISSCC, стр. 1-3. IEEE, (2015)Power Optimization for Pipelined ADCs with Open-Loop Residue Amplifiers., , , и . ICECS, стр. 132-135. IEEE, (2006)A 10b 20MS/s SAR ADC with a low-power and area-efficient DAC-compensated reference., , и . ESSCIRC, стр. 231-234. IEEE, (2017)A 0.0013mm2 10b 10MS/s SAR ADC with a 0.0048mm2 42dB-rejection passive FIR filter.. CICC, стр. 1-4. IEEE, (2018)Small-Area SAR ADCs With a Compact Unit-Length DAC Layout., , , и . IEEE Trans. Circuits Syst. II Express Briefs, 69 (10): 4038-4042 (2022)A Hybrid Design Automation Tool for SAR ADCs in IoT., , , , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 26 (12): 2853-2862 (2018)