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Disambiguation of "Portal, Jean-Michel"

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Implementation of Ternary Weights With Resistive RAM Using a Single Sense Operation Per Synapse.

, , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (1): 138-147 (2021)

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Jean-Michel Langlais

Jean-Michel Dengler

Jean-Michel Grossenbacher

Jean-Michel Autebert

Jean-Michel Ayache

 

Other publications of authors with the same name

Testing the Local Interconnect Resources of SRAM-Based FPGA's., , , and . J. Electron. Test., 16 (5): 513-520 (2000)Implementation of Ternary Weights with Resistive RAM Using a Single Sense Operation per Synapse., , , , , , , and . CoRR, (2020)Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications., , , , , , , , and . CoRR, (2020)Stochastic Computing for Hardware Implementation of Binarized Neural Networks., , , , , and . CoRR, (2019)A Novel Low Power Oriented Design Methodology for Analog Blocks., , , and . J. Low Power Electron., 4 (1): 60-67 (2008)Powering AI at the Edge: A Robust, Memristor-based Binarized Neural Network with Near-Memory Computing and Miniaturized Solar Cell., , , , , , , , , and 6 other author(s). CoRR, (2023)Model of the Weak Reset Process in HfOx Resistive Memory for Deep Learning Frameworks., , , , , , , , and . CoRR, (2021)Low cost built-in-tuning of on-chip passive filters for low-if double quadrature rf receiver., , , , and . LATS, page 1-4. IEEE Computer Society, (2015)Built-in tuning of RFIC Passive Polyphase Filter by process and thermal monitoring., , , , and . LATW, page 1-5. IEEE Computer Society, (2012)Infrastructure IP for Back-End Yield Improvement., , , and . ITC, page 1129-1134. IEEE Computer Society, (2003)