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Disambiguation of "Becker, Jürgen"

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A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s.

, , , , and . SoCC, page 294-299. IEEE, (2019)

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Jürgen Becker

Jürgen Becker

Jürgen Becker

Jürgen Becker

Jürgen Becker

 

Other publications of authors with the same name

A Reconfigurable Hardware-Monitor for Communication Analysis in Distributed Real-Time Systems., , and . IPPS/SPDP Workshops, volume 1388 of Lecture Notes in Computer Science, page 61-66. Springer, (1998)A Secure Framework with Remote Configuration of Intellectual Property., , and . ICISSP, page 564-571. SciTePress, (2019)A Hybrid Prototyping Framework in a Virtual Platform Centered Design and Verification Flow., , and . IEEE Embed. Syst. Lett., 13 (1): 1-4 (2021)From MOSFETs to Ambipolar Transistors: Standard Cell Synthesis for the Planar RFET Technology., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (1): 114-125 (2021)Providing multiple hard latency and throughput guarantees for packet switching networks on chip., , , and . Comput. Electr. Eng., 39 (8): 2603-2622 (2013)Work-in-Progress: Integrating WebAssembly into Service-Oriented Architectures for Edge Systems., , , and . EMSOFT, page 17-18. ACM / IEEE, (2023)Hardware-aware Workload Distribution for AI-based Online Handwriting Recognition in a Sensor Pen., , , , , , and . MECO, page 1-4. IEEE, (2022)Runtime Adaptive Cache Checkpointing for RISC Multi-Core Processors., , , , , and . SOCC, page 1-6. IEEE, (2022)Hypervisor-Based Target Deployment Strategies for Time Predictability in Model-Based Development., , and . SOCC, page 1-2. IEEE, (2022)SiFI-AI: A Fast and Flexible RTL Fault Simulation Framework Tailored for AI Models and Accelerators., , , , , and . ACM Great Lakes Symposium on VLSI, page 287-292. ACM, (2023)