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Overwrite Configuration Technique in Multicast Configuration Scheme for Dynamically Reconfigurable Processor Arrays., , , , , , and . FPT, page 273-276. IEEE, (2007)The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator., , and . FPT, page 1-4. IEEE, (2011)A low power reconfigurable accelerator using a back-gate bias control technique., , , and . FPT, page 390-393. IEEE, (2013)A speculative gather system for Cool Mega-Array., , , , , and . FPT, page 346-349. IEEE, (2013)Variable pipeline structure for Coarse Grained Reconfigurable Array CMA., , , and . FPT, page 217-220. IEEE, (2016)Acceleration of ART Algorithm on an FPGA Board with Xilinx SDAccel., and . CANDAR Workshops, page 280-284. IEEE, (2019)A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration., , and . MCSoC, page 32-37. IEEE, (2019)Proxy Responses by FPGA-Based Switch for MapReduce Stragglers., , , and . IEICE Trans. Inf. Syst., 101-D (9): 2258-2268 (2018)A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs., , , and . IEICE Trans. Inf. Syst., 90-D (12): 1914-1922 (2007)Foreword.. IEICE Trans. Inf. Syst., 95-D (12): 2749 (2012)