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Disambiguation of "Zambreno, Joseph"

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The design and integration of a software configurable and parallelized coprocessor architecture for LQR control.

, , , and . J. Parallel Distributed Comput., (2017)

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Stefanie Joseph

Virginia Joseph

Joseph Dehler

Joseph Ranft

Joseph Welsch

 

Other publications of authors with the same name

Scalable FastMDP for Pre-departure Airspace Reservation and Strategic De-conflict., , and . CoRR, (2020)Towards Reverse Engineering Controller Area Network Messages Using Machine Learning., , and . WF-IoT, page 1-6. IEEE, (2020)RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing., , , , and . IEEE Trans. Parallel Distributed Syst., 27 (10): 3029-3043 (2016)Enhancing Compiler Techniques for Memory Energy Optimizations., , and . EMSOFT, volume 2491 of Lecture Notes in Computer Science, page 364-381. Springer, (2002)An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (1): 113-123 (2012)A Reconfigurable Architecture for the Detection of Strongly Connected Components., , , and . ACM Trans. Reconfigurable Technol. Syst., 9 (2): 16:1-16:19 (2016)Improving System Predictability and Performance via Hardware Accelerated Data Structures., , , , , , and . ICCS, volume 9 of Procedia Computer Science, page 1197-1205. Elsevier, (2012)Design and Implementation of an FPGA Architecture for High-Speed Network Feature Extraction., , , , and . FPT, page 49-56. IEEE, (2007)k-NN text classification using an FPGA-based sparse matrix vector multiplication accelerator., , , , , and . EIT, page 257-263. IEEE, (2015)An FPGA-based Hardware Accelerator for Iris Segmentation., , and . ReConFig, page 1-8. IEEE, (2018)