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An efficient quadratic placement based on search space traversing technology.

, , , , and . Integr., 40 (3): 253-260 (2007)

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SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography., , and . ISQED, page 566-571. IEEE, (2013)Leakage power optimization for clock network using dual-Vth technology., , and . ISCAS, page 2769-2772. IEEE, (2008)SIAR: splitting-graph-based interactive analog router., , , and . ACM Great Lakes Symposium on VLSI, page 367-370. ACM, (2011)Evaluating a bounded slice-line grid assignment in O(nlogn) time., , , , , , and . ISCAS (4), page 708-711. IEEE, (2003)SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips., , , , and . ISPD, page 49-56. ACM, (2015)A thermal-driven force-directed floorplanning algorithm for 3D ICs., , , and . CAD/Graphics, page 497-502. IEEE, (2009)Optimization of via distribution and stacked via in multi-layered P/G networks., , and . Integr., 43 (3): 318-325 (2010)Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs., , , and . ASP-DAC, page 582-587. IEEE, (2006)Efficient model reduction of interconnects via double gramians approximation., , , and . ASP-DAC, page 25-30. IEEE, (2010)Application of optical proximity correction technology., , , , and . Sci. China Ser. F Inf. Sci., 51 (2): 213-224 (2008)