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Disambiguation of "Marques, Felipe S."

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Improving the methodology to build non-series-parallel transistor arrangements.

, , , , , and . SBCCI, page 1-6. IEEE, (2013)

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António Marques

Ricardo Marques

Miguel Marques

Nicolas Marques

Euro Marques

 

Other publications of authors with the same name

Fast disjoint transistor networks from BDDs., , , , , and . SBCCI, page 137-142. ACM, (2006)Post-processing of supergate networks aiming cell layout optimization., , , , , , and . ISCAS, page 1-4. IEEE, (2017)SmartDR: Algorithms and Techniques for Fast Detailed Routing with Good Design Rule Handling., , and . ACM Trans. Design Autom. Electr. Syst., 26 (2): 9:1-9:38 (2021)Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy., , , , , and . SBCCI, page 95-100. IEEE Computer Society, (2002)Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding., , , , and . MWSCAS, page 1-4. IEEE, (2016)Transistor-level optimization of CMOS complex gates., , , , , and . LASCAS, page 1-4. IEEE, (2013)Performance and Energy Consumption Analysis of Embedded Applications Based on Android Platform., , , , and . SBESC, page 59-64. IEEE Computer Society, (2012)Exploring Independent Gates in FinFET-Based Transistor Network Generation., , , , and . SBCCI, page 41:1-41:6. ACM, (2014)Improving the methodology to build non-series-parallel transistor arrangements., , , , , and . SBCCI, page 1-6. IEEE, (2013)Transistor Count Optimization in IG FinFET Network Design., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (9): 1483-1496 (2017)