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Disambiguation of "Bhadra, Jayanta"

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Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation.

, , , and . CHARME, volume 2144 of Lecture Notes in Computer Science, page 386-402. Springer, (2001)

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Jayanta Mondal

Jayanta Chatterjee

Jayanta Chattopadhyay

Jayanta Das

Marlies Luszik-Bhadra

 

Other publications of authors with the same name

Modeling and verification of industrial flash memories., , , and . ISQED, page 705-712. IEEE, (2010)Striking a balance between SoC security and debug requirements., and . SoCC, page 368-373. IEEE, (2016)Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation., , and . IEEE Des. Test Comput., 21 (6): 494-502 (2004)On application of data mining in functional debug., , , and . ICCAD, page 670-675. IEEE, (2014)A kernel-based approach for functional test program generation., , and . ITC, page 164-173. IEEE Computer Society, (2010)Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study., , , and . MTV, page 33-36. IEEE Computer Society, (2006)Challenges and Trends in Modern SoC Design Verification., , , , and . IEEE Des. Test, 34 (5): 7-22 (2017)A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor., , and . Formal Methods Syst. Des., 27 (1-2): 67-112 (2005)Introduction to special section on verification challenges in the concurrent world., , , , and . ACM Trans. Design Autom. Electr. Syst., 17 (3): 19:1-19:3 (2012)An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology., , , , and . ASP-DAC, page 163-168. IEEE, (2012)