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An error-correcting unordered code and hardware support for robust asynchronous global communication., и . DATE, стр. 765-770. IEEE Computer Society, (2010)A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems., , и . DATE, стр. 332-337. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Synthesis for Hazard-free Customized CMOS Complex-Gate Networks Under Multiple-Input Changes., , , и . DAC, стр. 77-82. ACM Press, (1996)An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 18 (7): 1043-1056 (2010)Synthesis for logical initializability of synchronous finite-state machines., и . IEEE Trans. Very Large Scale Integr. Syst., 8 (5): 542-557 (2000)Exact two-level minimization of hazard-free logic with multiple-input changes., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (8): 986-997 (1995)Guest Editorial., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (6): 662-664 (2003)A Flexible, Event-Driven Digital Filter With Frequency Response Independent of Input Sample Rate., , , и . IEEE J. Solid State Circuits, 49 (10): 2292-2304 (2014)A delay-insensitive bus-invert code and hardware support for robust asynchronous global communication., и . DATE, стр. 1370-1375. IEEE, (2011)Asynchronous Datapath with Software-Controlled On-Chip Adaptive Voltage Scaling for Multirate Signal Processing Application., , , , и . ASYNC, стр. 216-226. IEEE Computer Society, (2003)