( en | de | ru )

 

Disambiguation of "Chen, Tung-Chien"

Author of the publication

copydeleteadd this publication to your clipboard
A 473 μW wireless 16-channel neural recording SoC with RF energy harvester.

, , , , and . VLSI-DAT, page 1-4. IEEE, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Chen-Chien Li

Chien Fu Chen

Chien-An Chen

Tung-Sheng Chen

Chieh Chien

 

Other publications of authors with the same name

Exploration of reusing the pre-recorded training data set to improve the supervised classifier for EEG-based motor-imagery brain computer interfaces., , , , , and . ISCAS, page 2067-2070. IEEE, (2012)Robust heart rate measurement with phonocardiogram by on-line template extraction and matching., , , and . EMBC, page 1957-1960. IEEE, (2011)Assessing normality of heart sound by matching pursuit residue with frequency-domain-based templates., , and . EMBC, page 2917-2920. IEEE, (2012)Fast Algorithm and Architecture Design of Low-Power Integer Motion Estimation for H.264/AVC., , , , and . IEEE Trans. Circuits Syst. Video Techn., 17 (5): 568-577 (2007)Low power and power aware fractional motion estimation of H.264/AVC for mobile applications., , , and . ISCAS, IEEE, (2006)Design and implementation of a low power spike detection processor for 128-channel spike sorting microsystem., , and . ICASSP, page 3889-3892. IEEE, (2014)Analysis and Design of On-sensor ECG Processors for Realtime Detection of Cardiac Anomalies Including VF, VT, and PVC., , , , , , , and . J. Signal Process. Syst., 65 (2): 275-285 (2011)System Bandwidth Analysis of Multiview Video Coding with Precedence Constraint., , , , , and . ISCAS, page 1001-1004. IEEE, (2007)Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture., , and . ISCAS (2), page 273-276. IEEE, (2004)A 473 μW wireless 16-channel neural recording SoC with RF energy harvester., , , , and . VLSI-DAT, page 1-4. IEEE, (2018)