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Disambiguation of "Seznec, André"

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An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors.

, , and . Int. J. Parallel Program., 29 (1): 35-58 (2001)

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Janina Seznec

Karl Wilhelm Andrée

Emil Andrée

Gustav André

Michael André

 

Other publications of authors with the same name

Topic 08+13: Instruction-Level Parallelism and Computer Architecture., , , , , , , and . Euro-Par, volume 2150 of Lecture Notes in Computer Science, page 385. Springer, (2001)Data Synchronized Pipeline Architecture: Pipelining in Multiprocessor Environments., and . J. Parallel Distributed Comput., 3 (4): 508-526 (1986)Optimizing Memory Throughput In a Tightly Coupled Multiprocessor., and . ICPP, page 344-346. Pennsylvania State University Press, (1987)On the Interactions Between Value Prediction and Compiler Optimizations in the Context of EOLE., , and . ACM Trans. Archit. Code Optim., 14 (2): 18:1-18:24 (2017)DITVA: Dynamic Inter-Thread Vectorization Architecture., , , and . J. Parallel Distributed Comput., (2018)Fetch Gating Control through Speculative Instruction Window Weighting., and . Trans. High Perform. Embed. Archit. Compil., (2009)HAVEGE: A user-level software heuristic for generating empirically strong random numbers., and . ACM Trans. Model. Comput. Simul., 13 (4): 334-346 (2003)Fetch Gating Control Through Speculative Instruction Window Weighting., and . HiPEAC, volume 4367 of Lecture Notes in Computer Science, page 120-135. Springer, (2007)Odd Memory Systems May be Quite Interesting., and . ISCA, page 341-350. ACM, (1993)Effective ahead Pipelining of Instruction Block Address Generation., and . ISCA, page 241-252. IEEE Computer Society, (2003)