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Disambiguation of "Wu, Kai-Chiang"

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Aging-aware timing analysis and optimization considering path sensitization.

, and . DATE, page 1572-1577. IEEE, (2011)

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Kai-Yuan Wu

Chiang Liang

Chiang Mai

Joanna Chiang

Tzu-Chiang Chen

 

Other publications of authors with the same name

Aging-aware chip health prediction adopting an innovative monitoring strategy., , , and . ASP-DAC, page 179-184. ACM, (2019)Clock skew scheduling for soft-error-tolerant sequential circuits., and . DATE, page 717-722. IEEE Computer Society, (2010)Analysis and optimization of variable-latency designs in the presence of timing variability., , , and . DATE, page 1219-1224. IEEE, (2017)FLORA: Fine-grained Low-Rank Architecture Search for Vision Transformer., , , , , and . CoRR, (2023)Contouring Control of Smooth Paths for Multiaxis Motion Systems Based on Equivalent Errors., and . IEEE Trans. Contr. Sys. Techn., 15 (6): 1151-1158 (2007)Layout-Based Dual-Cell-Aware Tests., , , , , , , , , and . VTS, page 1-6. IEEE, (2019)Highly Uniform All-Vacuum-Deposited Inorganic Perovskite Artificial Synapses for Reservoir Computing., , , , , , , , and . Adv. Intell. Syst., 3 (1): 2000196 (2021)FOX-NAS: Fast, On-device and Explainable Neural Architecture Search., , , , , and . ICCVW, page 789-797. IEEE, (2021)ONNC Compiler Used in Fault-Mitigating Mechanisms Analysis on NVDLA-Based and ReRAM-Based Edge AI Chip Design., , , , , , and . VLSI-DAT, page 1-7. IEEE, (2021)Fast WAT test structure for measuring Vt variance based on latch-based comparators., , , and . VTS, page 1-6. IEEE Computer Society, (2017)