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Disambiguation of "Lee, Juhyoung"

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Z-PIM: A Sparsity-Aware Processing-in-Memory Architecture With Fully Variable Weight Bit-Precision for Energy-Efficient Deep Neural Networks.

, , , , and . IEEE J. Solid State Circuits, 56 (4): 1093-1104 (2021)

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Xavier Lee Lee

Bongsoo Lee

The role of negative regulators in coordination of the Myxococcus xanthus developmental program. Uni Marburg, (2009)

Min-Hi Lee

Induction and regulation of antiviral defence mechanisms through intracytoplasmic sensors. HU Berlin, (2009)

Sangbok Lee

Clara Lee

 

Other publications of authors with the same name

SNPU: An Energy-Efficient Spike Domain Deep-Neural-Network Processor With Two-Step Spike Encoding and Shift-and-Accumulation Unit., , , , , and . IEEE J. Solid State Circuits, 58 (10): 2812-2825 (October 2023)ECIM: Exponent Computing in Memory for an Energy-Efficient Heterogeneous Floating-Point DNN Training Processor., , , , , and . IEEE Micro, 42 (1): 99-107 (2022)NeRPIM: A 4.2 mJ/frame Neural Rendering Processing-in-memory Processor with Space Encoding Block-wise Mapping for Mobile Devices., , , , , , and . VLSI Technology and Circuits, page 1-2. IEEE, (2023)PNNPU: A Fast and Efficient 3D Point Cloud-based Neural Network Processor with Block-based Point Processing for Regular DRAM Access., , , and . HCS, page 1-23. IEEE, (2021)An Energy-efficient Floating-Point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory., , , , , , , and . HCS, page 1-20. IEEE, (2021)A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory., , , , , , and . VLSI Circuits, page 1-2. IEEE, (2021)OmniDRL: A 29.3 TFLOPS/W Deep Reinforcement Learning Processor with Dualmode Weight Compression and On-chip Sparse Weight Transposer., , , , , , and . VLSI Circuits, page 1-2. IEEE, (2021)An Energy-Efficient Deep Neural Network Training Processor with Bit-Slice-Level Reconfigurability and Sparsity Exploitation., , , , , , and . COOL CHIPS, page 1-3. IEEE, (2021)A Full HD 60 fps CNN Super Resolution Processor with Selective Caching based Layer Fusion for Mobile Devices., , , , , and . VLSI Circuits, page 302-. IEEE, (2019)7.4 GANPU: A 135TFLOPS/W Multi-DNN Training Processor for GANs with Speculative Dual-Sparsity Exploitation., , , , , , and . ISSCC, page 140-142. IEEE, (2020)