Author of the publication

Efficient test compression technique based on block merging.

. IET Comput. Digit. Tech., 2 (5): 327-335 (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Efficient test compression technique based on block merging.. IET Comput. Digit. Tech., 2 (5): 327-335 (2008)Test data compression for system-on-a-chip using extended frequency-directed run-length code.. IET Comput. Digit. Tech., 2 (3): 155-163 (2008)Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (11): 2556-2564 (2006)A probabilistic pairwise swap search state assignment algorithm for sequential circuit optimization.. Integr., (2017)A static test compaction technique for combinational circuits based on independent fault clustering., and . ICECS, page 1316-1319. IEEE, (2003)Simulated evolution algorithm for multiobjective VLSI netlist bi-partitioning., , and . ISCAS (5), page 457-460. IEEE, (2003)Simulation-Based Method for Synthesizing Soft Error Tolerant Combinational Circuits., and . IEEE Trans. Reliab., 64 (3): 935-948 (2015)Enhancing performance of iterative heuristics for VLSI netlist partitioning., , and . ICECS, page 507-510. IEEE, (2003)State assignment for power optimization of sequential circuits based on a probabilistic pairwise swap search algorithm.. ISSPIT, page 305-308. IEEE Computer Society, (2015)Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement., , , and . ICCD, page 484-487. IEEE Computer Society, (2001)