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TheSPoT: Thermal Stress-Aware Power and Temperature Management for Multiprocessor Systems-on-Chip.

, , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (8): 1532-1545 (2018)

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WL-VC SRAM: a low leakage memory circuit for deep sub-micron design., , and . ISCAS, IEEE, (2006)Systematic test program generation for SoC testing using embedded processor., , , and . ISCAS (5), page 541-544. IEEE, (2003)High performance circuit techniques for dynamic OR gates., , and . ISCAS, IEEE, (2006)Low Power Combinational Multipliers using Data-driven Signal Gating., and . APCCAS, page 1430-1433. IEEE, (2006)An Efficient Clocking Scheme for On-Chip Communications., , , and . APCCAS, page 119-122. IEEE, (2006)BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture., , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (2): 302-306 (2009)ByZFAD: a low switching activity architecture for shift-and-add multipliers., , and . SBCCI, page 179-183. ACM, (2006)An efficient network on-chip architecture based on isolating local and non-local communications., , , and . DATE, page 350-353. EDA Consortium San Jose, CA, USA / ACM DL, (2013)An efficent dynamic multicast routing protocol for distributing traffic in NOCs., , , , , , and . DATE, page 1064-1069. IEEE, (2009)Pipeline Event-driven No-race Charge recycling Logic (PENCL) for low power application., and . ICECS, page 220-223. IEEE, (2003)