( en | de | ru )

 

Disambiguation of "Pandya, Paritosh K."

Author of the publication

copydeleteadd this publication to your clipboard
Logics Meet 1-Clock Alternating Timed Automata.

, , and . CONCUR, volume 118 of LIPIcs, page 39:1-39:17. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Shreekrishna Pandya

Paritosh Padhy

Navinchandra Chimanlal Pandya

Paritosh Kumar Saha

Paritosh Kumar Das Gupta

 

Other publications of authors with the same name

Logical specification and uniform synthesis of robust controllers., and . MEMOCODE, page 15:1-15:11. ACM, (2019)DCSYNTH: Guided Reactive Synthesis with Soft Requirements for Robust Controller and Shield Synthesis., , and . CoRR, (2017)Finding Response Times in a Real-Time System., and . Comput. J., 29 (5): 390-395 (1986)Metric Temporal Logic with Counting., , and . CoRR, (2015)Deterministic Logics for UL., and . CoRR, (2014)ICSP and Its Relationship with ACSP and CSP., and . FSTTCS, volume 761 of Lecture Notes in Computer Science, page 358-372. Springer, (1993)Formal Design of Hybrid Systems., , , and . FTRTFT, volume 863 of Lecture Notes in Computer Science, page 738-755. Springer, (1994)On Construction of Safety Signal Automata for $MITL\: U, \: S$ Using Temporal Projections., , and . FORMATS, volume 6919 of Lecture Notes in Computer Science, page 225-239. Springer, (2011)Timed Automata with Integer Resets: Language Inclusion and Expressiveness., , , and . FORMATS, volume 5215 of Lecture Notes in Computer Science, page 78-92. Springer, (2008)Unambiguity in Timed Regular Languages: Automata and Logics., and . FORMATS, volume 6246 of Lecture Notes in Computer Science, page 168-182. Springer, (2010)