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Disambiguation of "Sinkar, Abhishek A."

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False Path Aware Timing Yield Estimation under Variability.

, , , and . VTS, page 161-166. IEEE Computer Society, (2009)

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Abhishek Mitra

Abhishek Bichhawat

Abhishek Banerjee

Abhishek Kumar

Chintagunta Abhishek

 

Other publications of authors with the same name

Combating Aging with the Colt Duty Cycle Equalizer., , , and . MICRO, page 103-114. IEEE Computer Society, (2010)Clamping Virtual Supply Voltage of Power-Gated Circuits for Active Leakage Reduction and Gate-Oxide Reliability., , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (3): 580-584 (2013)WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements., , and . VLSI Design, page 479-484. IEEE Computer Society, (2009)False Path Aware Timing Yield Estimation under Variability., , , and . VTS, page 161-166. IEEE Computer Society, (2009)AVS-aware power-gate sizing for maximum performance and power efficiency of power-constrained processors., and . ASP-DAC, page 725-730. IEEE, (2011)Improving platform energy: chip area trade-off in near-threshold computing environment., , and . ICCAD, page 318-325. IEEE, (2013)Maximizing Frequency and Yield of Power-Constrained Designs Using Programmable Power-Gating., , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (10): 1885-1890 (2012)Cost-effective power delivery to support per-core voltage domains for power-constrained processors., , , and . DAC, page 56-61. ACM, (2012)Analyzing potential power reduction with adaptive voltage positioning optimized for multicore processors., and . ISLPED, page 189-194. ACM, (2009)Statistical static timing analysis considering leakage variability in power gated designs., , , , and . ISLPED, page 57-62. ACM, (2009)