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Characterizing Individual Gate Power Sensitivity in Low Power Design.

, , and . VLSI Design, page 625-. IEEE Computer Society, (1999)

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Test compaction for sequential circuits., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 11 (2): 260-267 (1992)Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (5): 531-546 (1995)The Best Flip-Flops to Scan., , and . ITC, page 166-173. IEEE Computer Society, (1991)Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (9): 1141-1154 (1995)Synchronous Test Generation Model for Asynchronous Circuits., , and . VLSI Design, page 178-185. IEEE Computer Society, (1996)Impact of Partial Reset on Fault Independent Testing and BIST., , and . VLSI Design, page 537-539. IEEE Computer Society, (1997)T5: Low-Power Design., , , and . VLSI Design, page 4. IEEE Computer Society, (1997)Initialization Isuues in the Synthesis of Asynchronous Circuits., , , and . ICCD, page 447-452. IEEE Computer Society, (1994)Concurrent Error Detection in Nonlinear Digital Circuits with Applications to Adaptive Filters., and . ICCD, page 606-609. IEEE Computer Society, (1993)Initialization issues in asynchronous circuit synthesis., , and . J. Electron. Test., 9 (3): 237-250 (1996)