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Mixed-signal on-chip timing measurements.. Integr., 26 (1-2): 151-165 (1998)A BIST Design of Structured Arrays with Fault-Tolerant Layout., и . ITC, стр. 514-521. IEEE Computer Society, (1988)Test set selection for structural faults in analog IC's., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (7): 1026-1039 (1999)Extraction of instantaneous and RMS sinusoidal jitter using an analytic signal method., , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 50 (6): 288-298 (2003)Mismatch-Tolerant Circuit for On-Chip Measurements of Data Jitter., , , и . CICC, стр. 161-164. IEEE, (2007)An equivalent-time and clocked approach for continuous-time quantization., , , , , , , и . ISCAS, стр. 2529-2532. IEEE, (2011)Minimal overhead modification of iterative logic arrays for C-testability., и . ITC, стр. 964-969. IEEE Computer Society, (1990)Dynamic Testing of ADCs Using Wavelet Transforms., и . ITC, стр. 379-388. IEEE Computer Society, (1997)Data jitter measurement using a delta-time-to-voltage converter method., , , и . ITC, стр. 1-7. IEEE Computer Society, (2007)Testing clock distribution circuits using an analytic signal method., , , , , и . ITC, стр. 323-331. IEEE Computer Society, (2001)