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Hardware Virtual Components Compliant with Communication System Standards.

, , , , , , , and . DSD, page 88-95. IEEE Computer Society, (2005)

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Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis., , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (11): 1454-1464 (2008)An efficient algorithm for custom instruction enumeration., and . ACM Great Lakes Symposium on VLSI, page 187-192. ACM, (2011)A formal method for hardware IP design and integration under I/O and timing constraints., , , , and . ACM Trans. Embed. Comput. Syst., 5 (1): 29-53 (2006)Algorithms with improved delay for enumerating connected induced subgraphs of a large cardinality., , and . Inf. Process. Lett., (January 2024)An algorithm with improved delay for enumerating connected induced subgraphs of a large cardinality., , and . CoRR, (2021)Energy-Aware Partial-Duplication Task Mapping Under Real-Time and Reliability Constraints., , , and . SAMOS, volume 12471 of Lecture Notes in Computer Science, page 213-227. Springer, (2020)Orcc's compa-backend demonstration., , , , , , , , and . DASIP, page 1-2. IEEE, (2014)Place Reservation technique for online task placement on a multi-context heterogeneous reconfigurable architecture., , and . ReConFig, page 1-6. IEEE, (2014)Design of a flexible 2-D discrete wavelet transform IP core for JPEG2000 image coding in embedded imaging systems., , and . Signal Process., 86 (7): 1375-1399 (2006)Architectural Synthesis with Interconnection Cost Control., , and . VLSI, volume 162 of IFIP Conference Proceedings, page 509-520. Kluwer, (1999)