( en | de | ru )

 

Disambiguation of "Tesolin, Francesco"

Author of the publication

copydeleteadd this publication to your clipboard
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter.

, , , , , , , , , , , , , and . ISSCC, page 445-447. IEEE, (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Francesco Bettella

Protein secondary structure prediction using optimized scoring functions: a comparative statistical method. FU Berlin, (2009)

Francesco Knechtli

Francesco Pinosa

Francesco Solimena

Francesco Bagorda

 

Other publications of authors with the same name

10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM., , , , , , , and . ISSCC, page 188-190. IEEE, (2024)A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays., , , , , , , and . IEEE J. Solid State Circuits, 58 (9): 2466-2477 (September 2023)32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays., , , , , , , , , and 5 other author(s). ISSCC, page 456-458. IEEE, (2021)A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter., , , , , , , , , and 4 other author(s). ISSCC, page 445-447. IEEE, (2021)A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping., , , , , , , , , and 4 other author(s). IEEE J. Solid State Circuits, 57 (6): 1723-1735 (2022)A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 58 (3): 634-646 (March 2023)A Novel Topology of Coupled Phase-Locked Loops., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (3): 989-997 (2021)A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering., , , , , , , , , and 1 other author(s). ISSCC, page 78-79. IEEE, (2023)A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector., , , , , , and . CICC, page 1-2. IEEE, (2024)A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC., , , , , , and . CICC, page 1-2. IEEE, (2024)