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Enabling Internet-of-Things: Opportunities brought by emerging devices, circuits, and architectures.

X. Li, K. Ma, S. George, J. Sampson, and V. Narayanan. VLSI-SoC, page 1-6. IEEE, (2016)

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Sumitha Mohan

George Mertzios

Combinatorial optimization and recognition of graph classes with applications to related modelsG. Mertzios. TU Aachen, (2009)

Witold George

Hans George

George Glowik

Other publications of authors with the same name

A Module-Level Configuration Methodology for Programmable Camouflaged Logic.J. Wang, Z. Chen, J. Zhang, Y. Xu, T. Yu, Z. Zheng, E. Ye, S. George, H. Yang, Y. Liu and 3 other author(s). ACM Trans. Design Autom. Electr. Syst., 29 (2): 39:1-39:31 (March 2024)Adaptable Multi-level Voltage to Binary Converter Using Ferroelectric FETs.S. Das, A. Govindankutty, S. Deng, K. Ni, and S. George. ISVLSI, page 116-121. IEEE, (2022)MDACache: Caching for Multi-Dimensional-Access Memories.S. George, M. Liao, H. Jiang, J. Kotra, M. Kandemir, J. Sampson, and V. Narayanan. MICRO, page 841-854. IEEE Computer Society, (2018)Harnessing ferroelectrics for non-volatile memories and logic.S. Gupta, D. Wang, S. George, A. Aziz, X. Li, S. Datta, and V. Narayanan. ISQED, page 29-34. IEEE, (2017)Hardware Functional Obfuscation With Ferroelectric Active Interconnects.T. Yu, Y. Xu, S. Deng, Z. Zhao, N. Jao, Y. Kim, S. Dünkel, S. Beyer, K. Ni, S. George and 1 other author(s). CoRR, (2021)Ferroelectric FET based Context-Switching FPGA Enabling Dynamic Reconfiguration for Adaptive Deep Learning Machines.Y. Xu, Z. Zhao, Y. Xiao, T. Yu, H. Mulaosmanovic, D. Kleimaier, S. Dünkel, S. Beyer, X. Gong, R. Joshi and 9 other author(s). CoRR, (2022)A Compact Ferroelectric 2T-(n+1)C Cell to Implement AND-OR Logic in Memory.Y. Xiao, Y. Xu, S. Deng, Z. Zhao, S. George, K. Ni, and V. Narayanan. ISVLSI, page 1-6. IEEE, (2023)Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops.X. Li, S. George, K. Ma, W. Tsai, A. Aziz, J. Sampson, S. Gupta, M. Chang, Y. Liu, S. Datta and 1 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (11): 2907-2919 (2017)Ternary In-Memory Computing with Cryogenic Quantum Anomalous Hall Effect Memories.A. Govindankutty, S. Alam, S. Das, N. Challapalle, A. Aziz, and S. George. ACM Great Lakes Symposium on VLSI, page 521-526. ACM, (2023)Design Exploration of Dynamic Multi-Level Ternary Content-Addressable Memory Using Nanoelectromechanical Relays.T. Li, H. Zhong, S. George, V. Narayanan, L. Shi, H. Yang, and X. Li. ISVLSI, page 1-6. IEEE, (2023)

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Disambiguation of "George, Sumitha"

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Enabling Internet-of-Things: Opportunities brought by emerging devices, circuits, and architectures.

Please choose a person to relate this publication to

Sumitha Mohan

George Mertzios

Witold George

Hans George

George Glowik

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "George, Sumitha"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Enabling Internet-of-Things: Opportunities brought by emerging devices, circuits, and architectures.

Please choose a person to relate this publication to

Sumitha Mohan

George Mertzios

Witold George

Hans George

George Glowik

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Enabling Internet-of-Things: Opportunities brought by emerging devices, circuits, and architectures.