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A tool flow for predicting system level timing failures due to interconnect reliability degradation.

, , , , , и . ACM Great Lakes Symposium on VLSI, стр. 291-296. ACM, (2008)

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Georgios Papanikolaou

Paschalis Papanikolaou

Apostolos Papanikolaou

Amalia Papanikolaou

Antonis Tsiongas

 

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