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Другие публикации лиц с тем же именем

Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients., , и . VTS, стр. 64-69. IEEE Computer Society, (2011)A PAM-4 10S/12S line coding scheme with equi-probable levels., , , и . ISCAS, стр. 1-5. IEEE, (2018)SEU Tolerant Robust Latch Design., , , и . VDAT, том 7373 из Lecture Notes in Computer Science, стр. 223-232. Springer, (2012)Instruction-Based Self-Testing of Delay Faults in Pipelined Processors., , , и . IEEE Trans. Very Large Scale Integr. Syst., 14 (11): 1203-1215 (2006)Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients., , и . J. Electron. Test., 28 (5): 757-771 (2012)Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design., , , и . J. Electron. Test., 34 (1): 53-65 (2018)Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing., , и . J. Electron. Test., 28 (4): 541-549 (2012)REMO: Redundant execution with minimum area, power, performance overhead fault tolerant architecture., и . IOLTS, стр. 109-114. IEEE, (2016)Soft-error reliable architecture for future microprocessors., и . IET Comput. Digit. Tech., 13 (3): 233-242 (2019)A Framework for Configurable Joint-Scan Design-for-Test Architecture., , , и . J. Electron. Test., 37 (5): 593-611 (2021)