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Statistical modeling and analysis of chip-level leakage power by spectral stochastic method.

, , , , and . ASP-DAC, page 161-166. IEEE, (2009)

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Parallelizing SAT-based de-camouflaging attacks by circuit partitioning and conflict avoiding., , , and . Integr., (2019)Toward a Formal and Quantitative Evaluation Framework for Circuit Obfuscation Methods., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (10): 1844-1857 (2019)UTACO: a unified timing and congestion optimizing algorithm for standard cell global routing., , , , , , and . ASP-DAC, page 834-839. ACM, (2003)Static Probability Analysis Guided RTL Hardware Trojan Test Generation., , and . ASP-DAC, page 510-515. ACM, (2023)A Power Grids Electromigration Analysis with Via Array Using Current-Tracing Model., , and . ISCAS, page 1-5. IEEE, (2021)Improved multilevel routing with redundant via placement for yield and reliability., , , and . ACM Great Lakes Symposium on VLSI, page 143-146. ACM, (2005)Physical aware clock skew rescheduling., , and . ACM Great Lakes Symposium on VLSI, page 473-476. ACM, (2007)Register placement for low power clock network., , , , , , and . ASP-DAC, page 588-593. ACM Press, (2005)Logic and Layout Aware Voltage Island Generation for Low Power Design., , , and . ASP-DAC, page 666-671. IEEE Computer Society, (2007)Fast congestion-aware timing-driven placement for island FPGA., , and . DDECS, page 24-27. IEEE Computer Society, (2009)