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Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems.

, , and . DSD, page 229-232. IEEE Computer Society, (2009)

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On automatic software-based self-test program generation based on high-level decision diagrams., , and . LATS, page 177. IEEE, (2016)Evolutionary Approach to Test Generation for Functional BIST, , , , and . CoRR, (2010)PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams., , , and . J. Electron. Test., 25 (6): 289-300 (2009)Automated Design Error Localization in RTL Designs., , , , , , , , and . IEEE Des. Test, 31 (1): 83-92 (2014)Automated design error debug using high-level decision diagrams and mutation operators., , , , , and . Microprocess. Microsystems, 37 (4-5): 505-513 (2013)Representing Gate-Level SET Faults by Multiple SEU Faults at RTL., , , and . CoRR, (2021)Laboratory framework TEAM for investigating the dependability issues of microprocessor systems., , , and . EWME, page 80-83. IEEE, (2014)Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation., , and . ISCAS, page 1-5. IEEE, (2018)Hierarchical Identification of Untestable Faults in Sequential Circuits., , , and . DSD, page 668-671. IEEE Computer Society, (2007)Fault Diagnosis in Integrated Circuits with BIST., , , , and . DSD, page 604-610. IEEE Computer Society, (2007)