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Disambiguation of "Sieiro, Javier J."

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Optimized passive devices for low-power LNA design.

, , , and . ICECS, page 90-93. IEEE, (2010)

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Javier Manero

Javier Jáurequi

Javier Dreyer

Javier Papa

Javier Arpón

 

Other publications of authors with the same name

Quasi-static PEEC planar solver using a weighted combination of 2D and 3D analytical Green's functions and a predictive meshing generator., , , , , , and . Integr., (2018)Low-power current-reused RF front-end based on optimized transformers topology., , , and . Integr., 43 (2): 230-236 (2010)Compact class-AB follower for wideband closed loop line drivers., , and . ICECS, page 101-104. IEEE, (2012)Optimized passive devices for low-power LNA design., , , and . ICECS, page 90-93. IEEE, (2010)An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 36 (1): 15-26 (2017)Fabrication of Full-3D Printed Electronics RF Passive Components and Circuits., , , , , and . PRIME, page 265-268. IEEE, (2018)Introduction to the special issue on Radio Frequency Integrated Circuits (RFIC) design techniques., and . Integr., (2016)Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (8): 1269-1273 (2014)Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology., , , , , , , , and . IEEE Access, (2020)Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop., , , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (6): 989-1002 (2019)