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Microscopic scale characterization and modeling of transistor degradation under HC stress., , , , , , , and . Microelectron. Reliab., 52 (11): 2513-2520 (2012)Advanced TCAD for predictive FinFETs Vth mismatch using full 3D process/device simulation., , , , , , , , , and . ESSDERC, page 341-344. IEEE, (2014)Novel Back Gate Doping Ultra Low Retention Power 22nm FDSOl SRAM for IOT Application., , , , , , , , , and 13 other author(s). ESSDERC, page 78-81. IEEE, (2018)Comparison of Analog and Noise Performance between Buried Channel versus Surface Devices in HKMG I/O Devices., , , , , , , , , and 3 other author(s). IRPS, page 1-4. IEEE, (2021)22FDX® fMAX Optimization through Parasitics Reduction and GM Boost., , , , , , , , , and 8 other author(s). ESSDERC, page 166-169. IEEE, (2019)Low-Frequency Noise Reduction in 22FDX®: Impact of Device Geometry and Back Bias., , , , , , , , and . IRPS, page 1-5. IEEE, (2019)Design Optimization of MV-NMOS for ESD Self-protection in 28nm CMOS technology., , , , , , , and . IRPS, page 1-4. IEEE, (2020)Impact of Electrical Defects located at Transistor Periphery on Analog and RTN Device Performance., , , , , , , , , and 2 other author(s). IRPS, page 59-1. IEEE, (2022)RTN and LFN Noise Performance in Advanced FDSOI Technology., , , , , , , , , and 2 other author(s). ESSDERC, page 254-257. IEEE, (2018)