( en | de | ru )

 

Disambiguation of "Pekmestzi, Kiamal Z."

Author of the publication

copydeleteadd this publication to your clipboard
High performance MAC designs.

, , , and . IDT, page 30-35. IEEE, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Z Taufig

Bence Z Szalai

Leonardo Quevedo Z

Milorad Z Djordjevic

ir Z hid

 

Other publications of authors with the same name

On the design of modulo 2n±1 residue generators., , , and . VLSI-SoC, page 33-38. IEEE, (2013)Efficient support vector machines implementation on Intel/Movidius Myriad 2., , , , , and . MOCAST, page 1-4. IEEE, (2018)A bit-interleaved systolic architecture for a high-speed RSA system., and . Integr., 30 (2): 169-175 (2001)Pipelined array-based FIR filter folding., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 52-I (1): 108-118 (2005)VOSsim: A Framework for Enabling Fast Voltage Overscaling Simulation for Approximate Computing Circuits., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (6): 1204-1208 (2018)On the Diminished-1 Modulo 2n+1 Addition and Subtraction., , and . J. Circuits Syst. Comput., 29 (5): 2030005:1-2030005:14 (2020)A segmentation-based BISR scheme., , , , and . ASP-DAC, page 652-657. IEEE, (2014)Multi-Level Approximate Accelerator Synthesis Under Voltage Island Constraints., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (4): 607-611 (2019)Modulo 2n ± 1 Fused Add-Multiply Units., , , and . ISVLSI, page 91-96. IEEE Computer Society, (2015)High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures., , , and . ISVLSI, page 486-487. IEEE Computer Society, (2010)