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Disambiguation of "Ferrandi, Fabrizio"

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An Efficient Heuristic Approach to Solve the Unate Covering Problem.

, , , and . DATE, page 364-371. IEEE Computer Society / ACM, (2000)

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Fabrizio Catanese

Fabrizio Gabbiani

Fabrizio Gabrielli

Fabrizio Lindner

Fabrizio Arosio

 

Other publications of authors with the same name

Symbolic Optimization of FSM Networks Based on Sequential ATPG Techniques., , , , and . DAC, page 467-470. ACM Press, (1996)Bambu: A modular framework for the high level synthesis of memory-intensive applications., and . FPL, page 1-4. IEEE, (2013)Performance modeling of embedded applications with zero architectural knowledge., and . CODES+ISSS, page 277-286. ACM, (2010)HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms., , , , , , , , , and 1 other author(s). IEEE Micro, 30 (5): 88-97 (2010)Enabling Automated Bug Detection for IP-Based Designs Using High-Level Synthesis., , and . IEEE Des. Test, 35 (5): 54-62 (2018)SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels., , , , , , , , , and 3 other author(s). ARCS Workshops, VDE-Verlag, (2011)Symbolic optimization of interacting controllers based onredundancy identification and removal., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (7): 760-772 (2000)A design methodology to implement memory accesses in high-level synthesis., , and . CODES+ISSS, page 49-58. ACM, (2011)An Interrupt Controller for FPGA-based Multiprocessors., , , , , , and . ICSAMOS, page 82-87. IEEE, (2007)Hardware DWT accelerator for MultiProcessor System-on-Chip on FPGA., , , , , , and . ICSAMOS, page 107-114. IEEE, (2006)