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A fast error correction technique for matrix multiplication algorithms.

, , , and . IOLTS, page 133-137. IEEE Computer Society, (2009)

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On a Class of Fault-Tolerant Multiprocessor Network Architectures.. ICDCS, page 302-311. IEEE Computer Society, (1982)Wormhole routing in de Bruijn networks and hyper-de Bruijn networks., and . ISCAS (3), page 870-873. IEEE, (2003)Soft Error Mitigation in Switch Modules of SRAM-based FPGAs., , , and . ISCAS, page 141-144. IEEE, (2007)CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs., , , and . ISCAS, page 3675-3678. IEEE, (2007)Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment., , and . DAC, page 414-419. ACM Press, (1995)Modeling Live and Dead Lines in Cache Memory Systems., , and . IEEE Trans. Computers, 42 (1): 1-14 (1993)Store Address Generator with On-Line Fault-Detection Capability., , and . IEEE Trans. Computers, 26 (11): 1144-1151 (1977)The Effect of Program Behavior on Fault Observability., and . IEEE Trans. Computers, 45 (8): 868-880 (1996)Roll-Forward and Rollback Recovery: Performance-Reliability Trade-Off., and . IEEE Trans. Computers, 46 (3): 372-378 (1997)The De Bruijn Multiprocessor Network: A Versatile Parallel Processing and Sorting Network for VLSI., and . IEEE Trans. Computers, 38 (4): 567-581 (1989)Correction: IEEE Transactions on Computers 41(1): 122-123 (1991).