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Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors.

, , , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (4): 747-758 (2014)

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Low-Cost Per-Core Voltage Domain Support for Power-Constrained High-Performance Processors., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (4): 747-758 (2014)High Performance Mathematical Quarter-Pixel Motion Estimation with Novel Rate Distortion Metric for H.264/AVC., , , and . CSICC, volume 6 of Communications in Computer and Information Science, page 219-226. (2008)Minimizing total area of low-voltage SRAM arrays through joint optimization of cell size, redundancy, and ECC., , , , and . ICCD, page 112-117. IEEE Computer Society, (2010)Augmenting general purpose processors for network processing., , , and . FPT, page 416-419. IEEE, (2003)An Effective VHDL-AMS Simulation Algorithm with Event Partitioning., and . VLSI Design, page 762-767. IEEE Computer Society, (2005)Muli-Issue Multi-Threaded Stream Processor., , and . ICME, page 2041-2044. IEEE Computer Society, (2006)Comparison of single-ISA heterogeneous versus wide dynamic range processors for mobile applications., , and . ICCD, page 304-310. IEEE Computer Society, (2015)Workload-adaptive process tuning strategy for power-efficient multi-core processors., , , , , and . ISLPED, page 225-230. ACM, (2010)Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors., , and . HPCA, page 38-49. IEEE Computer Society, (2011)VR-scale: runtime dynamic phase scaling of processor voltage regulators for improving power efficiency., , , , and . DAC, page 151:1-151:6. ACM, (2016)