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An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function.

, , and . VLSI Design, page 615-620. IEEE Computer Society, (2007)

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SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test & Variation Tolerant Design., , , and . CICC, page 547-554. IEEE, (2006)Analysis of super cut-off transistors for ultralow power digital logic circuits., , , and . ISLPED, page 2-7. ACM, (2006)Multi-scale Fusion Dynamic Graph Neural Network For Traffic Flow Prediction., , , , and . ADMIT, page 85-90. ACM, (2023)Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS., , , and . VTS, page 292-297. IEEE Computer Society, (2005)Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations., , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (11): 1286-1295 (2005)Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design., , , and . DATE, page 983-988. European Design and Automation Association, Leuven, Belgium, (2006)A Soft Error Monitor Using Switching Current Detection., , , and . ICCD, page 185-192. IEEE Computer Society, (2005)A novel synthesis approach for active leakage power reduction using dynamic supply gating., , , , and . DAC, page 479-484. ACM, (2005)Process Variation Tolerant Online Current Monitor for Robust Systems., , , and . IOLTS, page 171-176. IEEE Computer Society, (2005)Energy recovery clocked dynamic logic., , , and . ACM Great Lakes Symposium on VLSI, page 468-471. ACM, (2005)