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Efficient serial and parallel implementation of programmable fir filters based on the merging technique.

, , and . EUSIPCO, page 1-5. IEEE, (2008)

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Efficient implementation of biomedical hardware using open source descriptions and behavioral synthesis.. BIBE, page 1-6. IEEE, (2008)Design and experimentation with low-power morphable multipliers., , , and . ICECS, page 752-755. IEEE, (2011)High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures., , , and . ISVLSI, page 486-487. IEEE Computer Society, (2010)Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures., , , , and . ISVLSI, page 133-138. IEEE Computer Society, (2010)High-level synthesis with coarse grain reconfigurable components., and . IPDPS, page 1-4. IEEE, (2009)Efficient serial and parallel implementation of programmable fir filters based on the merging technique., , and . EUSIPCO, page 1-5. IEEE, (2008)HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips., , , , and . IPDPS Workshops, page 2194-2199. IEEE, (2013)A complete specification and implementation methodology for high-level hardware transformations., , and . ICECS, page 520-523. IEEE, (2000)Exploiting the Use of VHDL Specifications in the AGENDA High-Level Synthesis Environment., and . EUROMICRO, page 10091-10098. IEEE Computer Society, (1998)BIT-width exploration over 3D architectures using high-level synthesis., , , and . ICECS, page 535-538. IEEE, (2010)