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Exploratory Power Noise Models of Standard Cell 14, 10, and 7 nm FinFET ICs.

, , , and . ACM Great Lakes Symposium on VLSI, page 233-238. ACM, (2016)

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Crosstalk modeling for coupled RLC interconnects with application to shield insertion., and . IEEE Trans. Very Large Scale Integr. Syst., 14 (6): 641-646 (2006)Effects of inductance on the propagation delay and repeater insertion in VLSI circuits., and . IEEE Trans. Very Large Scale Integr. Syst., 8 (2): 195-206 (2000)Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling., , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (10): 1559-1564 (2009)Multi-aggressor capacitive and inductive coupling noise modeling and mitigation., , and . Microelectron. J., 43 (4): 235-243 (2012)Monolithic voltage conversion in low-voltage CMOS technologies., , , and . Microelectron. J., 36 (9): 863-867 (2005)Clock tree layout design for reduced delay uncertainty., , and . SoCC, page 179-180. IEEE, (2004)Low power repeaters driving RC interconnects with delay and bandwidth constraints., and . SoCC, page 335-339. IEEE, (2004)Signal waveform characterization in RLC trees., , and . ISCAS (6), page 190-193. IEEE, (1999)Inductive interconnect width optimization for low power., and . ISCAS (5), page 273-276. IEEE, (2003)Decoupling technique and crosstalk analysis for coupled RLC interconnects., and . ISCAS (2), page 521-524. IEEE, (2004)