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Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors.

, and . CHES, volume 4249 of Lecture Notes in Computer Science, page 270-284. Springer, (2006)

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VLSI Implementation of a Functional Unit to Accelerate ECC and AES on 32-Bit Processors., and . WAIFI, volume 4547 of Lecture Notes in Computer Science, page 40-54. Springer, (2007)Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors., and . CHES, volume 4249 of Lecture Notes in Computer Science, page 270-284. Springer, (2006)Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box., , and . SAMOS, volume 4017 of Lecture Notes in Computer Science, page 457-466. Springer, (2006)Architectural Enhancements to Support Digital Signal Processing and Public-Key Cryptography., , and . WISES, page 129-143. Graz University of Technology, (2004)Hardware Implementation of the SHA-3 Candidate Skein.. IACR Cryptology ePrint Archive, (2009)High-Speed Hardware Implementations of BLAKE, Blue Midnight Wish, CubeHash, ECHO, Fugue, Gröstl, Hamsi, JH, Keccak, Luffa, Shabal, SHAvite-3, SIMD, and Skein., , , , , and . IACR Cryptology ePrint Archive, (2009)Compact Hardware Implementations of the SHA-3 Candidates ARIRANG, BLAKE, Gröstl, and Skein., , , , , , , , , and . IACR Cryptology ePrint Archive, (2009)Energy-Efficient Software Implementation of Long Integer Modular Arithmetic., , , and . CHES, volume 3659 of Lecture Notes in Computer Science, page 75-90. Springer, (2005)Power Analysis Resistant AES Implementation with Instruction Set Extensions., and . CHES, volume 4727 of Lecture Notes in Computer Science, page 303-319. Springer, (2007)SCA-resistant embedded processors: the next generation., , and . ACSAC, page 211-220. ACM, (2010)